1. Field of the Invention
The present invention relates to a processing apparatus and control method thereof for carrying out a floating point multiply-add operation, and more particularly, to a processing apparatus and control method thereof suitable for use in Taylor series operations.
2. Description of the Related Art
A mathematical function f(x) can be expressed by a Taylor series operation as shown in Formula (1) below.
Therefore, a value of the mathematical function f(x) for an arbitrary value x can be obtained by performing a Taylor series operation in Formula (1).
      f    ⁡          (      x      )        =            ∑      n        ⁢                  1                  n          !                    ⁢                                    f                          (              n              )                                ⁡                      (                          x              0                        )                          ·                              (                          x              -                              x                0                                      )                    n                    
Here, coefficient data
      1          n      !        ⁢            f              (        n        )              ⁡          (              x        0            )      of the Taylor series operation expressed by above described Formula (1) varies depending on the type of the mathematical function f(x) and the degree of Taylor series.
For this reason, the conventional processing apparatus stores the Taylor series coefficient data associated with the mathematical function f(x) and degree in a memory (main memory) using a table model.
When the value of the mathematical function f(x) is calculated through a Taylor series operation, necessary coefficient data is read from the memory.
As described above, the conventional processing apparatus stores coefficient data necessary for a Taylor series operation of a mathematical function in a memory.
Therefore, when executing Taylor series operation processing, the conventional processing apparatus executes a floating point load instruction, loads the coefficient data from the memory into a register and then executes a floating point multiply-add instruction and performs a Taylor series operation using the coefficient data loaded into the register.
FIG. 8 shows the system configuration of a processing apparatus provided with a conventional Taylor series operation function.
A conventional processing apparatus 2000 shown in FIG. 8 performs a Taylor series operation of a mathematical function by executing a floating point multiply-add instruction 2010 shown on the left of FIG. 8.
The floating point multiply-add instruction 2010 is made up of five fields 2011 to 2015.
An “instruction type code (floating point multiply-add instruction code)” is set in the field 2011, a “one input register number of multiply operation of multiply-add operation” is set in the field 2012 and the “other input register number of multiply operation of multiply-add operation” is set in the field 2013.
Furthermore, the “input register number of add operation of multiply-add operation” is set in the field 2014 and the “output register number of operation result of multiply-add operation” is set in the field 2015.
A register number is a number uniquely assigned to each register.
When the floating point multiply-add instruction 2010 is decoded, the value (assumed to be data y) of a register with register number r1 set in the field 2012 (hereinafter referred to as “register r1”) is read from the register 2020 and the data y is inputted to the floating point multiply-adder 2040 through a multiplexer 2031.
Furthermore, the value (assumed to be data z) of a register with register number r2 set in the field 2013 (hereinafter referred to as “register r2”) is read from the register 2020 and the data z is inputted to the floating point multiply-adder 2040 through a multiplexer 2032.
Furthermore, the value (assumed to be data ai) of a register with register number r3 set in the field 2014 (hereinafter referred to as “register r3”) is read from the register 2020 and the data ai is inputted to the floating point multiply-adder 2040 through a multiplexer 2033.
Upon receiving the above described three pieces of data y, z and ai as input, the floating point multiply-adder 2040 performs floating point multiply-add operation of (y×z+ai) and writes the operation result into the register of register number w1 set in the field 2015 (hereinafter referred to as “register w1”) through a multiplexer 2034.
The processing apparatus 2000 repeatedly executes the floating point multiply-add instruction 2010 every time the floating point multiply-add instruction 2010 for a Taylor series operation program is fetched, thereby performs a Taylor series operation of mathematical function and calculates a value of the mathematical function f(x).
As described above, since the conventional processing apparatus 2000 stores coefficient data of a Taylor series of mathematical function in the main memory, it would perform a Taylor series multiply-add operation using a floating point load instruction and a floating point multiply-add instruction.
This produces overhead caused by processing of transferring Taylor series coefficient data from the main memory to a cache memory.
Furthermore, since the above described floating point load instruction needs to be executed, this puts pressure on throughput of a load/store pipeline or pressure on throughput of an instruction issue stage of an instruction pipeline, which becomes a factor that drives the deterioration of processing performance of a Taylor series operation.